113 research outputs found

    Time-sensitive Information Flow Control in Timed Event-B

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    Protecting confidential data in today’s computing\ud environments is an important problem. Information flow\ud control can help to avoid information leakage and violations\ud introduced by executing the software applications. In software\ud development cycle, it is important to handle security related\ud issues from the beginning specifications at the level of abstract.\ud Mu [1] investigated the problem of preserving information flow\ud security in the Event-B specification models. A typed Event-\ud B model was presented to enforce information flow security\ud and to prevent direct flows introduced by the system. However,\ud in practice, timing behaviours of programs can also introduce\ud a covert flow. The problem of run-time flow monitoring and\ud controlling must also be addressed. This paper investigates\ud information flow control in the Event-B specification language\ud with timing constructs. We present a timed Event-B system\ud by introducing timers and relevant time constraints into the\ud system events. We suggest a time-sensitive flow security condition\ud for the timed Event-B systems, and present a type system\ud to close the covert channels of timing flows for the system by\ud ensuring the security condition. We then investigate how to\ud refine timed events during the stepwise refinement modelling\ud to satisfy the security condition

    A Program Logic for Reasoning About C11 Programs With Release-Sequences

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    Learning Types for Binaries

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    Type Learning for Binaries and its Applications

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    State-Taint Analysis for Detecting Resource Bugs

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    Towards An Automated Approach to Hardware/Software Decomposition

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    We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog. Through this, we confirm successful verification for the correctness of the partitioning process by an algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.Singapore-MIT Alliance (SMA

    Automated verification of the freeRTOS scheduler in HIP/SLEEK

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    Automated verification of operating system kernels is a challenging problem, partly due to the use of shared mutable data structures. In this paper, we show how we can automatically verify memory safety and functional correctness of the task scheduler component of the FreeRTOS kernel using the verification system HIP/SLEEK. We show how some of HIP/SLEEK features like user-defined predicates and lemmas make the specifications highly expressive and the verification process viable. To the best of our knowledge, this is the first code-level verification of memory safety and functional correctness properties of the FreeRTOS scheduler. The outcome of our experiment confirms that HIP/SLEEK can indeed be used to verify code that is used in production. Moreover, since the properties that we verify are quite general, we envisage that the same approach can be adopted to verify the scheduler of other operating systems.(undefined

    Bi-Abductive Inference for Shape and Ordering Properties

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    Region Type Checking for Core-Java

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    Region-based memory management offers several important advantages over garbage-collected heap, including real-time performance, better data locality and efficient use of limited memory. The concept of regions was first introduced for a call-by-value functional language by Tofte and Talpin, and has since been advocated for imperative and object-oriented languages. Scope memory, a lexical variant of regions, is now a core feature in a recent proposal on Real-Time Specification for Java (RTSJ). In this paper, we propose a region-based memory management system for a core subset of Java. Our region type analysis can completely prevent dangling references and thus is ready to cater for the no-dangling requirement in RTSJ. Our system also supports modular compilation, which is an important feature for Java, but was missing in recent related work.Singapore-MIT Alliance (SMA
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